In an oversampling Clock and Data Recovery (CDR) system in which oversampling is more than twofold, two of the sampling clocks are positioned on each side of the average position of data edges in the serial input data by incrementing and decrementing the clock position to balance indications of late clocks and early clocks from the oversampling of the input stream. A lock is achieved when the clock position follows the average position of the data edge. The data is then preferably used from a sample made as centrally as possible between the noisy data edge positions. Two possible lock positions can be made. The CDR is “in lock” when the data is sampled centrally between the noisy data edge positions, but there is also an undesirable lock where the data sample is made in the middle of the noisy data edge position (a “false lock”).
Many phase locked control loops exhibit both the desirable stabel equilibrium position when the CDR is in lock and the unstable equilibrium condition, or false lock, when the CDR is 180° out of lock and is stuck sampling the data edge. In this unstable equilibrium condition it can take a significant amount of time for the instability to grow sufficiently for the phase locked loop to move to the proper in lock condition.
Conventionally the system is allowed to settle into a lock using the same method used to follow the average data edge position. This can cause a false lock for an underlying long time.
The conventional methods and apparatus of the prior art thus cannot prevent an oversampling clock and data recover system from attaining such a false lock and settling into a position in which sampling is stuck for an extended period in a position in which it is taking place at a data edge.